Reboot Timer

The sys.reboot property is used to engage a timer that reboots the system in a specified number of seconds. This can e.g. be used before experimenting with radio settings, to ensure the system returns to a working configuration. The reboot timer can not be enabled by default and will not erase any stored properties.

To enable it, set the sys.reboot property to the number of seconds until reboot. The property value can be read back and will decrement every second. To disable the timer, set the property to 0.

Watchdog Timer

External watchdog timers are connected to the SRX-8 microcontrollers. The watchdogs are automatically reset by the microcontrollers and require no configuration or control from the user.

Memory Protection

The FPGA configuration is protected against bit flips by the AMD Soft Error Mitigation (SEM) core [SEM]. Memories in the FPGA that are not protected by the SEM core (such as ROMs holding filter coefficients etc.) are protected by an Error-Correcting Code (ECC) similar to that of the SEM core. This Single Error Correction, Double Error Detection (SECDED) ECC is capable of correcting any single bit error and detecting any double bit errors.

Detected, corrected and uncorrectable bit flips are logged in tm.sem.* properties. The tm.sem.state property reflects the SEM core state. It should nominally be 2, indicating the core is in observation state.

The SEM telemetry values are currently purely observational, and the system will not perform any automatic actions, such as rebooting, in case of uncorrectable errors.